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The Cascaded Integrator-Comb (CIC) Filter

Block diagram of 3-stage CIC decimator
The Cascaded-Integrater-Comb filter is an efficient way of implementing lowpass filters and is particularly useful for sampling rate conversion using decimation or interpolation. The figure above shows a 3-stage CIC decimator, and illustrates the hardware simplicity: only six adders and six registers are required to implement decimation by an integer factor R.

I implemented a CIC filter in VHDL in a Xilinx FPGA for the open source MHZ100Q project. Code is available there, and documentation is being generated. MHZ100Q is a multipurpose data acquisition system that includes A/D converters running at a fixed 100MHz sampling rate with antialiasing filters that are appropriate for that rate. Lower-rate data is obtained by lowpass filtering and desampling inside the FPGA.

Another nice feature of CIC for this application is that the desampling factor depends only on the factor R in the diagram. The integrator part of the cascade (left half of the diagram) runs at the full 100MHz rate, while the comb part (the 3 differentiators in the right half) runs at the 1/R rate.

The first version of the MHZ100Q code included a multiplexer to bypass the CIC when the full 100MHz rate was desired. Then I realized that the bypass is unnecessary: if R is equal to 1, then the integrators and differentiators run at the same rate and cancel each other out.

More information

CIC filters were first described by Hogenauer in 1981. The Wikipedia page has a brief overview and some links for more information.

$Date: 2016/02/16 12:28:04 $